Static Random Access Memory (SRAM) is a type of memory that does not require periodic refreshing (as does DRAM), but retains its data as long as the power to the memory remains turned on.
Each bit in an SRAM is stored on four transistors that form two cross-coupled inverters. Access to the cell is enabled by the word line which controls two access transistors. These access transistors control whether the cell will be connected to the bit lines: BL and BL_bar. If the cell stores a 1, a read cycle is started by precharging both the bit lines to a logical 1, then asserting the word line WL, enabling both the access transistors. Next, the stored values are transferred to the bit lines by leaving BL at its precharged value and discharging BL_bar through the access transistors to a logical 0. The access transistors pull BL toward VDD, a logical 1. If the cell contains a 0, BL_bar is pulled toward 1 and BL toward 0. Then a sense amplifier will sense a small difference between BL and BL_bar, and determine which line has higher voltage. The sense amplifier thus determines whether a 1 or 0 was stored in the SRAM.
In the above-described read access cycle, all of the cells connected to the asserted word line WL are “developed”, and start to pull their respective bit lines from VDD to ground, by more than 100 millivolts. These “dummy reads” do not read data out of every bit cell connected to that word line, but they all contribute to active power consumption. Further, this pre-charge in all of the bit lines (BL and BL_bar) generates a large current and cause voltage drop and noise.